112 search results - page 3 / 23 » Performance Implications of Cache Affinity on Multicore Proc... |
ISPASS
2009
IEEE
14 years 17 days ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
HIPEAC
2010
Springer
14 years 2 months ago
2010
Springer
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
ISPASS
2010
IEEE
14 years 19 days ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
SODA
2008
ACM
13 years 7 months ago
2008
ACM
This paper presents a multicore-cache model that reflects the reality that multicore processors have both per-processor private (L1) caches and a large shared (L2) cache on chip. ...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...