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» Performance and Power Aware CMP Thread Allocation Modeling
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CASES
2006
ACM
13 years 11 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
GLOBECOM
2009
IEEE
14 years 2 days ago
Optimal Power Allocation Strategy Against Jamming Attacks Using the Colonel Blotto Game
Abstract—Cognitive radio technologies have become a promising approach to increase the efficiency of spectrum utilization. Although cognitive radio has been intensively studied ...
Yongle Wu, Beibei Wang, K. J. Ray Liu
JUCS
2000
120views more  JUCS 2000»
13 years 5 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
INFOCOM
2010
IEEE
13 years 3 months ago
Asymmetry-Aware Real-Time Distributed Joint Resource Allocation in IEEE 802.22 WRANs
—In IEEE 802.22 Wireless Regional Area Networks (WRANs), each Base Station (BS) solves a complex resource allocation problem of simultaneously determining the channel to reuse, p...
Hyoil Kim, Kang G. Shin
SIGMETRICS
2011
ACM
161views Hardware» more  SIGMETRICS 2011»
12 years 8 months ago
Modeling program resource demand using inherent program characteristics
The workloads in modern Chip-multiprocessors (CMP) are becoming increasingly diversified, creating different resource demands on hardware substrate. It is necessary to allocate h...
Jian Chen, Lizy Kurian John, Dimitris Kaseridis