Sciweavers

176 search results - page 1 / 36
» Performance improvement with circuit-level speculation
Sort
View
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 11 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ASPDAC
2008
ACM
116views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Faster projection based methods for circuit level verification
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...
Chao Yan, Mark R. Greenstreet
ICS
1999
Tsinghua U.
13 years 10 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
CCGRID
2003
IEEE
13 years 9 months ago
Kernel Level Speculative DSM
Interprocess communication (IPC) is ubiquitous in today's computing world. One of the simplest mechanisms for IPC is shared memory. We present a system that enhances the Syst...
Cristian Tapus
IEEEPACT
1999
IEEE
13 years 10 months ago
In Search of Speculative Thread-Level Parallelism
This paper focuses on the problem of how to find and effectively exploit speculative thread-level parallelism. Our studies show that speculating only on loops does not yield suffi...
Jeffrey T. Oplinger, David L. Heine, Monica S. Lam