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» Performance pathologies in hardware transactional memory
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BMCBI
2010
139views more  BMCBI 2010»
13 years 6 months ago
A highly efficient multi-core algorithm for clustering extremely large datasets
Background: In recent years, the demand for computational power in computational biology has increased due to rapidly growing data sets from microarray and other high-throughput t...
Johann M. Kraus, Hans A. Kestler
JSA
2008
91views more  JSA 2008»
13 years 6 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
ASPLOS
2006
ACM
14 years 1 days ago
AVIO: detecting atomicity violations via access interleaving invariants
Concurrency bugs are among the most difficult to test and diagnose of all software bugs. The multicore technology trend worsens this problem. Most previous concurrency bug detect...
Shan Lu, Joseph Tucek, Feng Qin, Yuanyuan Zhou
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 10 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
ICCSA
2007
Springer
14 years 6 days ago
FRASH: Hierarchical File System for FRAM and Flash
Abstract. In this work, we develop novel file system, FRASH, for byteaddressable NVRAM (FRAM[1]) and NAND Flash device. Byte addressable NVRAM and NAND Flash is typified by the DRA...
Eun-ki Kim, Hyungjong Shin, Byung-gil Jeon, Seokhe...