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PPOPP
2006
ACM
13 years 10 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
IEEEPACT
2008
IEEE
13 years 11 months ago
Multi-optimization power management for chip multiprocessors
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
PDPTA
2003
13 years 6 months ago
HPJava: Programming Support for High-Performance Grid-Enabled Applications
The paper begins by considering what a Grid Computing Environment might be, why it is demanded, and how the authors’ HPspmd programming fits into this picture. We then review o...
Han-Ku Lee, Bryan Carpenter, Geoffrey Fox, Sang Bo...
VEE
2012
ACM
234views Virtualization» more  VEE 2012»
12 years 13 days ago
REEact: a customizable virtual execution manager for multicore platforms
With the shift to many-core chip multiprocessors (CMPs), a critical issue is how to effectively coordinate and manage the execution of applications and hardware resources to overc...
Wei Wang, Tanima Dey, Ryan W. Moore, Mahmut Aktaso...
TC
2010
13 years 3 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers