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IEEEPACT
2008
IEEE
13 years 11 months ago
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aa...
MSWIM
2004
ACM
13 years 10 months ago
IEEE 802.11 rate adaptation: a practical approach
Today, three different physical (PHY) layers for the IEEE 802.11 WLAN are available (802.11a/b/g); they all provide multi-rate capabilities. To achieve a high performance under v...
Mathieu Lacage, Mohammad Hossein Manshaei, Thierry...
SIGARCH
2008
96views more  SIGARCH 2008»
13 years 5 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
HPCA
2004
IEEE
14 years 5 months ago
Accurate and Complexity-Effective Spatial Pattern Prediction
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas ...
PPOPP
1997
ACM
13 years 9 months ago
Performance Implications of Communication Mechanisms in All-Software Global Address Space Systems
Global addressing of shared data simplifies parallel programming and complements message passing models commonly found in distributed memory machines. A number of programming sys...
Beng-Hong Lim, Chi-Chao Chang, Grzegorz Czajkowski...