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CAV
1998
Springer
175views Hardware» more  CAV 1998»
13 years 9 months ago
An ACL2 Proof of Write Invalidate Cache Coherence
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
J. Strother Moore
CF
2008
ACM
13 years 7 months ago
Cell-SWat: modeling and scheduling wavefront computations on the cell broadband engine
This paper contributes and evaluates a model and a methodology for implementing parallel wavefront algorithms on the Cell Broadband Engine. Wavefront algorithms are vital in sever...
Ashwin M. Aji, Wu-chun Feng, Filip Blagojevic, Dim...
BMCBI
2006
99views more  BMCBI 2006»
13 years 5 months ago
MAGIC-SPP: a database-driven DNA sequence processing package with associated management tools
Background: Processing raw DNA sequence data is an especially challenging task for relatively small laboratories and core facilities that produce as many as 5000 or more DNA seque...
Chun Liang, Feng Sun, Haiming Wang, Junfeng Qu, Ro...
VLSISP
2008
100views more  VLSISP 2008»
13 years 5 months ago
Memory-constrained Block Processing for DSP Software Optimization
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattach...