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ISVLSI
2005
IEEE
69views VLSI» more  ISVLSI 2005»
13 years 10 months ago
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access con...
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, E...
RTSS
2009
IEEE
13 years 11 months ago
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, Ab...
PATMOS
2004
Springer
13 years 10 months ago
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the inï¬...
Eric Senn, Johann Laurent, Nathalie Julien, Eric M...
RSP
1999
IEEE
125views Control Systems» more  RSP 1999»
13 years 9 months ago
Extended Synchronous Dataflow for Efficient DSP System Prototyping
Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes...
Chanik Park, JaeWoong Chung, Soonhoi Ha
ICS
2003
Tsinghua U.
13 years 10 months ago
miNI: reducing network interface memory requirements with dynamic handle lookup
Recent work in low-latency, high-bandwidth communication systems has resulted in building user–level Network InControllers (NICs) and communication abstractions that support dir...
Reza Azimi, Angelos Bilas