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» Pipelined Packet-Forwarding Floating Point: II. An Adder
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ARITH
1997
IEEE
13 years 9 months ago
Pipelined Packet-Forwarding Floating Point: II. An Adder
Asger Munk Nielsen, David W. Matula, Chung Nan Lyu...
ARITH
2007
IEEE
13 years 11 months ago
Optimistic Parallelization of Floating-Point Accumulation
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
Nachiket Kapre, André DeHon
ERSA
2004
130views Hardware» more  ERSA 2004»
13 years 6 months ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
IPPS
2005
IEEE
13 years 10 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna