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» Polylogarithmic concurrent data structures from monotone cir...
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PODC
2009
ACM
14 years 5 months ago
Max registers, counters, and monotone circuits
A method is given for constructing a max register, a linearizable, wait-free concurrent data structure that supports a write operation and a read operation that returns the larges...
James Aspnes, Hagit Attiya, Keren Censor
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 8 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
IFIP
1992
Springer
13 years 8 months ago
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
Jochen Beister, Ralf Wollowski
ESA
2003
Springer
116views Algorithms» more  ESA 2003»
13 years 10 months ago
Smoothed Motion Complexity
We propose a new complexity measure for movement of objects, the smoothed motion complexity. Many applications are based on algorithms dealing with moving objects, but usually data...
Valentina Damerow, Friedhelm Meyer auf der Heide, ...