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» Postsilicon Validation Methodology for Microprocessors
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ISPASS
2005
IEEE
13 years 10 months ago
Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
Aashish Phansalkar, Ajay Joshi, Lieven Eeckhout, L...
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
13 years 11 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
IEEEPACT
2002
IEEE
13 years 9 months ago
Workload Design: Selecting Representative Program-Input Pairs
Having a representative workload of the target domain of a microprocessor is extremely important throughout its design. The composition of a workload involves two issues: (i) whic...
Lieven Eeckhout, Hans Vandierendonck, Koenraad De ...
ICCAD
2000
IEEE
102views Hardware» more  ICCAD 2000»
13 years 9 months ago
Provably Good Global Buffering Using an Available Buffer Block Plan
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...
IPCCC
1999
IEEE
13 years 9 months ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus