14 search results - page 2 / 3 » Power Aware Dividers in FPGA |
FPL
2007
Springer
13 years 12 months ago
2007
Springer
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
JNW
2007
13 years 5 months ago
2007
— This paper presents an optimization of PSM to improve its energy conservation. According to PSM, time is divided into beacon intervals. At the beginning of each beacon interval...
VLSID
2007
IEEE
14 years 6 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
FPL
2010
Springer
13 years 3 months ago
2010
Springer
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this work we consider battery powered portable systems which either have Field Programmable Gate Arrays (FPGA) or voltage and frequency scalable processors as their main proces...