178 search results - page 2 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
ASAP
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper reviews a set of techniques for compiling dataflow-based, graphical programs for embedded signal processing applications into efficient implementations on programmable ...
IEEEINTERACT
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper examines the effect of compiler optimizations on the energy usage and power consumption of the Intel Pentium 4 processor. We measure the effects of different levels of ...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
