178 search results - page 3 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
DATE
2002
IEEE
13 years 11 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
ASPDAC
1998
ACM
13 years 10 months ago
1998
ACM
We developed a new modular synthesis approach for design of low-power core-based data-intensive application-specific systems on silicon. The power optimization is conducted in th...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
DATE
2007
IEEE
14 years 11 days ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
CASES
2001
ACM
13 years 9 months ago
2001
ACM
It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, n...