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ICCD
2003
IEEE
112views Hardware» more  ICCD 2003»
14 years 1 months ago
Power Efficient Data Cache Designs
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
Jaume Abella, Antonio González
ISMVL
2005
IEEE
107views Hardware» more  ISMVL 2005»
13 years 10 months ago
Multiple-Valued Caches for Power-Efficient Embedded Systems
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
Emre Özer, Resit Sendag, David Gregg
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
CODES
2005
IEEE
13 years 6 months ago
An efficient direct mapped instruction cache for application-specific embedded systems
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
Chuanjun Zhang
IPCCC
2006
IEEE
13 years 11 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John