Multiple-Valued Caches for Power-Efficient Embedded Systems

In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded systems. Multiple-valued caches have significant potential for compact and powerefficient cache array design. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or a mix of both. Our analytical study of cache silicon area shows that an embedded System-on-achip (SoC) equipped with a multiple-valued cache model can reduce the cache data storage area up to 6% regardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued instruction cache in an embedded SoC.

• Type: Conference
• Year: 2005
• Where: ISMVL
• Authors: Emre Özer, Resit Sendag, David Gregg
• Keywords: Artificial Intelligence, Cache, Cache Energy Consumption, Cache Model, ISMVL 2005