3 search results - page 1 / 1 » Power and signal integrity improvement in ultra high-speed c... |
ISCAS
1999
IEEE
13 years 8 months ago
1999
IEEE
Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very ...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...