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DATE
2005
IEEE
98views Hardware» more  DATE 2005»
13 years 11 months ago
Hardware Accelerated Power Estimation
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
13 years 8 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 7 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
DELTA
2006
IEEE
13 years 11 months ago
Static Code Analysis of Functional Descriptions in SystemC
The co-design of hardware and software systems with object oriented design languages like SystemC has become very popular. Static analysis of those descriptions allows to conduct ...
Martin Holzer 0002, Markus Rupp
DAC
2005
ACM
14 years 6 months ago
Power emulation: a new paradigm for power estimation
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
Joel Coburn, Srivaths Ravi, Anand Raghunathan