17 search results - page 1 / 4 » Power performance hardware optimization for synchronization ... |
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
JSA
2010
12 years 11 months ago
2010
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Nowadays, in MPSoCs and NoCs, multicast protocol is significantly used for many parallel applications such as cache coherency in distributed shared-memory architectures, clock sync...