9 search results - page 2 / 2 » Power-Performance Implications of Thread-level Parallelism o... |
IISWC
2009
IEEE
13 years 12 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
IEEEPACT
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
DAMON
2006
Springer
13 years 9 months ago
2006
Springer
A new trend in processor design is increased on-chip support for multithreading in the form of both chip multiprocessors and simultaneous multithreading. Recent research in databa...
IWMM
2010
Springer
13 years 10 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...