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ISLPED
2010
ACM
193views Hardware» more  ISLPED 2010»
13 years 4 months ago
PASAP: power aware structured ASIC placement
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
Ashutosh Chakraborty, David Z. Pan
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 1 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
ASPLOS
2000
ACM
13 years 9 months ago
Power Aware Page Allocation
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory ...
Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schl...