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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
13 years 5 months ago
Practical Monte-Carlo based timing yield estimation of digital circuits
—The advanced sampling and variance reduction techniques as efficient alternatives to the slow crude-MC method have recently been adopted for the analysis of timing yield in dig...
Javid Jaffari, Mohab Anis
DATE
2008
IEEE
102views Hardware» more  DATE 2008»
13 years 11 months ago
A New Approach for Combining Yield and Performance in Behavioural Models for Analogue Integrated Circuits
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
13 years 10 months ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
TCAD
2010
164views more  TCAD 2010»
12 years 11 months ago
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
The Monte-Carlo (MC) technique is a traditional solution for a reliable statistical analysis, and in contrast to probabilistic methods, it can account for any complicate model. How...
Javid Jaffari, Mohab Anis
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
13 years 9 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen