20 search results - page 2 / 4 » Practical techniques to reduce skew and its variations in bu... |
TVLSI
2010
12 years 12 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approac...
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
INTEGRATION
2008
13 years 5 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
DAC
2010
ACM
13 years 3 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...