5 search results - page 1 / 1 » Practical variation-aware interconnect delay and slew analys... |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...