47 search results - page 1 / 10 » Precomputation-based Guarding for Dynamic and Leakage Power ... |
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...