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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICSE
2005
IEEE-ACM
14 years 6 months ago
Main effects screening: a distributed continuous quality assurance process for monitoring performance degradation in evolving so
Developers of highly configurable performanceintensive software systems often use a type of in-house performance-oriented "regression testing" to ensure that their modif...
Cemal Yilmaz, Arvind S. Krishna, Atif M. Memon, Ad...
ANCS
2005
ACM
13 years 11 months ago
Framework for supporting multi-service edge packet processing on network processors
Network edge packet-processing systems, as are commonly implemented on network processor platforms, are increasingly required to support a rich set of services. These multi-servic...
Arun Raghunath, Aaron R. Kunze, Erik J. Johnson, V...
IJES
2006
110views more  IJES 2006»
13 years 6 months ago
Partitioning bin-packing algorithms for distributed real-time systems
Embedded real-time systems must satisfy not only logical functional requirements but also para-functional properties such as timeliness, Quality of Service (QoS) and reliability. W...
Dionisio de Niz, Raj Rajkumar
LCTRTS
2010
Springer
14 years 24 days ago
Sampling-based program execution monitoring
For its high overall cost during product development, program debugging is an important aspect of system development. Debugging is a hard and complex activity, especially in time-...
Sebastian Fischmeister, Yanmeng Ba