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» Prediction of Power Requirements for High-Speed Circuits
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SIGCOMM
2009
ACM
13 years 11 months ago
Game action based power management for multiplayer online game
Current mobile devices embrace a wide range of functionalities including high speed network support, hardware accelerated 3D graphics, and multimedia capabilities. These capabilit...
Bhojan Anand, Akkihebbal L. Ananda, Mun Choon Chan...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
WSC
1998
13 years 6 months ago
SEAMS: Simulation Environment for VHDL-AMS
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
Peter Frey, Kathiresan Nellayappan, Vasudevan Sahn...
DAC
2001
ACM
14 years 6 months ago
Future Performance Challenges in Nanometer Design
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
Dennis Sylvester, Himanshu Kaul
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
13 years 11 months ago
Transition-aware decoupling-capacitor allocation in power noise reduction
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang