908 search results - page 181 / 182 » Predictive performance modelling of parallel component compo... |
ISCA
1997
IEEE
13 years 10 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
CP
2008
Springer
13 years 7 months ago
2008
Springer
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
EUROPAR
2009
Springer
13 years 10 months ago
2009
Springer
Data access in HPC infrastructures is realized via user-level networking and OS-bypass techniques through which nodes can communicate with high bandwidth and low-latency. Virtualiz...
SIGMOD
1996
ACM
13 years 10 months ago
1996
ACM
METU INteroperable Database System (MIND) is a multidatabase system that aims at achieving interoperability among heterogeneous, federated DBMSs. MIND architecture is based on OMG...
ICPP
2002
IEEE
13 years 10 months ago
2002
IEEE
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...