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DAC
1995
ACM
13 years 8 months ago
Register Allocation and Binding for Low Power
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
Jui-Ming Chang, Massoud Pedram
IPPS
2000
IEEE
13 years 9 months ago
Register Assignment for Software Pipelining with Partitioned Register Banks
Many techniques for increasing the amount of instruction-level parallelism (ILP) put increased pressure on the registers inside a CPU. These techniques allow for more operations t...
Jason Hiser, Steve Carr, Philip H. Sweany, Steven ...
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 6 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
13 years 9 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
CASES
2005
ACM
13 years 6 months ago
A post-compilation register reassignment technique for improving hamming distance code compression
Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most op...
Montserrat Ros, Peter Sutton