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DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 3 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
AE
2005
Springer
13 years 10 months ago
Evolutionary Design of a DDPD Model of Ligation
Ligation is a form of chemical self-assembly that involves dynamic formation of strong covalent bonds in the presence of weak associative forces. We study an extremely simple form ...
Mark A. Bedau, Andrew Buchanan, Gianluca Gazzola, ...
IWSOC
2003
IEEE
99views Hardware» more  IWSOC 2003»
13 years 10 months ago
Template Generation and Selection Algorithms
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a template generation method to extra...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Pa...
ICIP
2003
IEEE
14 years 6 months ago
Optimal steerable filters for feature detection
We present a new approach for the design of optimal steerable 2-D templates for feature detection. As opposed to classical schemes where the optimal 1-D template is derived and ex...
Mathews Jacob, Michael Unser
SCIE
1997
Springer
13 years 8 months ago
Semantic Matching: Formal Ontological Distinctions for Information Organization, Extraction, and Integration
Abstract. The task of information extraction can be seen as a problem of semantic matching between a user-defined template and a piece of information written in natural language. T...
Nicola Guarino