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» Priority-based high-speed switch scheduling for ATM networks
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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
13 years 11 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ASPLOS
1992
ACM
13 years 9 months ago
High Speed Switch Scheduling for Local Area Networks
Current technology trends make it possible to build communication networks that can support high performance distributed computing. This paper describes issues in the design of a ...
Thomas E. Anderson, Susan S. Owicki, James B. Saxe...
ISCAPDCS
2004
13 years 6 months ago
A New Multicast Queuing Mechanism for High-Speed Packet Switches
Increasing multimedia applications such as teleconferencing and video-on-demand require the Internet to effectively provide high-performance multicast support. One of the promisin...
Min Song, Sachin Shetty, Mansoor Alam, HouJun Yang
ICPP
1999
IEEE
13 years 9 months ago
New Delay Analysis in High Speed Networks
The implementation of bounded-delay services over integrated services networks relies admission control mechanisms that in turn use end-to-end delay computation algorithms. For gu...
Chengzhi Li, Riccardo Bettati, Wei Zhao
INFOCOM
2000
IEEE
13 years 10 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin