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» Probabilistic Analysis of Rectilinear Steiner Trees
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VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
14 years 5 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
13 years 10 months ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 6 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
COMGEO
2004
ACM
13 years 4 months ago
Expected time analysis for Delaunay point location
We consider point location in Delaunay triangulations with the aid of simple data structures. In particular, we analyze methods in which a simple data structure is used to first lo...
Luc Devroye, Christophe Lemaire, Jean-Michel Morea...