Sciweavers

129 search results - page 25 / 26
» Process Variations and their Impact on Circuit Operation
Sort
View
FASE
2006
Springer
13 years 9 months ago
Trace-Based Memory Aliasing Across Program Versions
One of the major costs of software development is associated with testing and validation of successive versions of software systems. An important problem encountered in testing and...
Murali Krishna Ramanathan, Suresh Jagannathan, Ana...
CCR
2004
116views more  CCR 2004»
13 years 6 months ago
End-to-end congestion control for TCP-friendly flows with variable packet size
Current TCP-friendly congestion control mechanisms adjust the packet rate in order to adapt to network conditions and obtain a throughput not exceeding that of a TCP connection op...
Jörg Widmer, Catherine Boutremans, Jean-Yves ...
ASPDAC
2005
ACM
140views Hardware» more  ASPDAC 2005»
13 years 11 months ago
A multi-level transmission line network approach for multi-giga hertz clock distribution
-In high performance systems, process variations and fluctuations of operating environments have significant impact on the clock skew. Recently, hybrid structures of H-tree and m...
Hongyu Chen, Chung-Kuan Cheng
DAC
2002
ACM
14 years 7 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
HPCA
2006
IEEE
14 years 6 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...