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DATE
2008
IEEE
78views Hardware» more  DATE 2008»
13 years 11 months ago
Transistor-Specific Delay Modeling for SSTA
SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, varia...
Brian Cline, Kaviraj Chopra, David Blaauw, Andres ...
ATS
2010
IEEE
229views Hardware» more  ATS 2010»
13 years 2 months ago
Variation-Aware Fault Modeling
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
Fabian Hopsch, Bernd Becker, Sybille Hellebrand, I...
ICCD
2007
IEEE
111views Hardware» more  ICCD 2007»
14 years 1 months ago
On modeling impact of sub-wavelength lithography on transistors
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Aswin Sreedhar, Sandip Kundu
CODES
2010
IEEE
13 years 2 months ago
Statistical approach in a system level methodology to deal with process variation
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
Concepción Sanz Pineda, Manuel Prieto, Jos&...
DAC
2008
ACM
14 years 5 months ago
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires at...
Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao