40 search results - page 8 / 8 » Process variation tolerant low power DCT architecture |
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
INFOCOM
2002
IEEE
13 years 9 months ago
2002
IEEE
— We consider the problem of distributing high-quality video signals over IP multicast in large Local Area Networks (LANs), under realtime delay constraints, and with software-on...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
DSN
2007
IEEE
13 years 11 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...