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CGO
2004
IEEE
13 years 8 months ago
Static Identification of Delinquent Loads
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
HPCA
2005
IEEE
14 years 5 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ICC
2009
IEEE
150views Communications» more  ICC 2009»
13 years 11 months ago
Optimum Internet Gateway Selection in Ad Hoc Networks
—Wireless ad hoc networks are connected to the fixed Internet by means of Internet gateways. Whenever a node within the ad hoc network wishes to communicate with a host in the I...
Felix Hoffmann, Daniel Medina
ASPLOS
2004
ACM
13 years 10 months ago
Scalable selective re-execution for EDGE architectures
Pipeline flushes are becoming increasingly expensive in modern microprocessors with large instruction windows and deep pipelines. Selective re-execution is a technique that can r...
Rajagopalan Desikan, Simha Sethumadhavan, Doug Bur...
IADIS
2004
13 years 6 months ago
Selecting Multimedia Interactions to Build Knowledge Structures
Two sets of multimedia learning materials were compared for their ability to promote learning of introductory computer programming The first set of materials was a sequentially na...
Wendy Doube, Juhani Tuovinen, Dale Shaffer