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» Programmable Active Memories: A Performance Assessment
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ISPASS
2010
IEEE
13 years 8 months ago
Understanding transactional memory performance
Abstract—Transactional memory promises to generalize transactional programming to mainstream languages and data structures. The purported benefit of transactions is that they ar...
Donald E. Porter, Emmett Witchel
APVIS
2006
13 years 7 months ago
Predicting graph reading performance: a cognitive approach
Performance and preference measures are commonly used in the assessment of visualization techniques. This is important and useful in understanding differences in effectiveness bet...
Weidong Huang, Seok-Hee Hong, Peter Eades
MVA
1992
188views Computer Vision» more  MVA 1992»
13 years 7 months ago
The Programmable and Configurable Low Level Vision Unit of the HERMIA Machine
In this work the Low Level Vision Unit (LLVU) of the Heterogeneous and Reconfigurable Machine for Image Analysis (HERMIA) is described. The LLVU consists of the innovative integra...
Gaetano Gerardi, Giancarlo Parodi
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
14 years 2 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
13 years 9 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim