44 search results - page 3 / 9 » Programmable Hardware Implementation for the Median-Rational... |
TC
2011
12 years 11 months ago
2011
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
ERSA
2009
13 years 3 months ago
2009
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
ISCAS
2011
IEEE
12 years 9 months ago
2011
IEEE
— we present an implementation of a programmable axonal propagation delay circuit which uses one first-order logdomain low-pass filter. Delays may be programmed in the 550ms rang...