Sciweavers

38 search results - page 3 / 8
» Programmable logic circuits based on ambipolar CNFET
Sort
View
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
13 years 10 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ITCC
2002
IEEE
13 years 10 months ago
FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition
: Since modern programmable devices contain embedded memory blocks, there exists a possibility to implement Finite State Machines (FSM) using such blocks. The size of the memory av...
Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
FPL
2003
Springer
81views Hardware» more  FPL 2003»
13 years 10 months ago
A TCP/IP Based Multi-device Programming Circuit
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
David V. Schuehler, Harvey Ku, John W. Lockwood
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
13 years 11 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
13 years 10 months ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko