We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
: Since modern programmable devices contain embedded memory blocks, there exists a possibility to implement Finite State Machines (FSM) using such blocks. The size of the memory av...
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...