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VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
14 years 5 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 2 months ago
Optimizing yield in global routing
We present the first efficient approach to global routing that takes spacing-dependent costs into account and provably finds a near-optimum solution including these costs. We sh...
Dirk Müller
STOC
2001
ACM
122views Algorithms» more  STOC 2001»
14 years 5 months ago
Provisioning a virtual private network: a network design problem for multicommodity flow
Consider a setting in which a group of nodes, situated in a large underlying network, wishes to reserve bandwidth on which to support communication. Virtual private networks (VPNs...
Anupam Gupta, Jon M. Kleinberg, Amit Kumar, Rajeev...
DAC
2009
ACM
14 years 6 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert