129 search results - page 1 / 26 » Providing Automated Verification in HOL Using MDGs |
ATVA
2004
Springer
13 years 8 months ago
2004
Springer
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
TPHOL
2000
IEEE
13 years 8 months ago
2000
IEEE
The IA-64 architecture defers floating point and integer division to software. To ensure correctness and maximum efficiency, Intel provides a number of recommended algorithms which...
JSA
2008
13 years 4 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
CIIA
2009
13 years 6 months ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
CADE
2008
Springer
14 years 5 months ago
2008
Springer
We present a tool for automatic generation of packed bitfields and tagged unions for systems-level C, along with automatic, machine checked refinement proofs in Isabelle/HOL. Our a...