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DAC
2010
ACM
13 years 6 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
BMCBI
2007
104views more  BMCBI 2007»
13 years 5 months ago
TISs-ST: a web server to evaluate polymorphic translation initiation sites and their reflections on the secretory targets
Background: The nucleotide sequence flanking the translation initiation codon (start codon context) affects the translational efficiency of eukaryotic mRNAs, and may indicate the ...
Renato Vicentini, Marcelo Menossi
CF
2009
ACM
14 years 8 days ago
A light-weight fairness mechanism for chip multiprocessor memory systems
Chip Multiprocessor (CMP) memory systems suffer from the effects of destructive thread interference. This interference reduces performance predictability because it depends heavil...
Magnus Jahre, Lasse Natvig
COMSWARE
2007
IEEE
14 years 3 days ago
On Optimal Performance in Mobile Ad hoc Networks
In this paper we are concerned with finding the maximum throughput that a mobile ad hoc network can support. Even when nodes are stationary, the problem of determining the capaci...
Tapas K. Patra, Joy Kuri, Pavan Nuggehalli
AVI
2008
13 years 8 months ago
Agent warp engine: formula based shape warping for networked applications
Computer visualization and networking have advanced dramatically over the last few years, partially driven by the exploding video game market. 3D hardware acceleration has reached...
Alexander Repenning, Andri Ioannidou