41 search results - page 8 / 9 » Quantifying Error in Dynamic Power Estimation of CMOS Circui... |
DAC
2004
ACM
14 years 6 months ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
ISQED
2007
IEEE
14 years 1 days ago
2007
IEEE
Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and accurate...
ICCAD
2008
IEEE
14 years 6 days ago
2008
IEEE
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
DSN
2004
IEEE
13 years 9 months ago
2004
IEEE
The relentless scaling of CMOS technology has provided a steady increase in processor performance for the past three decades. However, increased power densities (hence temperature...
ISCAS
1999
IEEE
13 years 10 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...