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» Quantum logic synthesis by symbolic reachability analysis
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DATE
2009
IEEE
163views Hardware» more  DATE 2009»
14 years 3 days ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
LICS
2003
IEEE
13 years 10 months ago
Model checking for probability and time: from theory to practice
Probability features increasingly often in software and hardware systems: it is used in distributed co-ordination and routing problems, to model fault-tolerance and performance, a...
Marta Z. Kwiatkowska
DAC
2006
ACM
14 years 6 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
ENTCS
2007
178views more  ENTCS 2007»
13 years 5 months ago
Recent Advances in Real-Time Maude
This paper gives an overview of recent advances in Real-Time Maude. Real-Time Maude extends the Maude rewriting logic tool to support formal specification and analysis of object-...
Peter Csaba Ölveczky, José Meseguer
ESOP
2008
Springer
13 years 7 months ago
Verification of Higher-Order Computation: A Game-Semantic Approach
Abstract. We survey recent developments in an approach to the verification of higher-order computation based on game semantics. Higherorder recursion schemes are in essence (progra...
C.-H. Luke Ong