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DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 10 days ago
Timing-reasoning-based delay fault diagnosis
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizin...
Kai Yang, Kwang-Ting Cheng
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
14 years 13 days ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
QEST
2010
IEEE
13 years 4 months ago
On the Theory of Stochastic Processors
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
Parasara Sridhar Duggirala, Sayan Mitra, Rakesh Ku...
TVLSI
2010
13 years 29 days ago
Asynchronous Current Mode Serial Communication
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam ...
RTSS
2005
IEEE
13 years 12 months ago
Decentralized Utilization Control in Distributed Real-Time Systems
Many real-time systems must control their CPU utilizations in order to meet end-to-end deadlines and prevent overload. Utilization control is particularly challenging in distribut...
Xiaorui Wang, Dong Jia, Chenyang Lu, Xenofon D. Ko...