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ICPPW
2005
IEEE
13 years 10 months ago
Performance Evaluation of High-Speed Interconnects Using Dense Communication Patterns
We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these int...
Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Siv...
TC
2008
13 years 5 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
DAC
2002
ACM
14 years 6 months ago
A physical model for the transient response of capacitively loaded distributed rlc interconnects
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
PE
2008
Springer
143views Optimization» more  PE 2008»
13 years 5 months ago
Improving the performance of large interconnection networks using congestion-control mechanisms
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
José Miguel-Alonso, Cruz Izu, José-&...
SIGCOMM
2006
ACM
13 years 11 months ago
In VINI veritas: realistic and controlled network experimentation
This paper describes VINI, a virtual network infrastructure that allows network researchers to evaluate their protocols and services in a realistic environment that also provides ...
Andy C. Bavier, Nick Feamster, Mark Huang, Larry L...