We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these int...
Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Siv...
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
As the size of parallel computers increases, as well as the number of sources per router node, congestion inside the interconnection network rises significantly. In such systems, ...
This paper describes VINI, a virtual network infrastructure that allows network researchers to evaluate their protocols and services in a realistic environment that also provides ...
Andy C. Bavier, Nick Feamster, Mark Huang, Larry L...