4 search results - page 1 / 1 » Realization of a Novel Fault Tolerant Reversible Full Adder ... |
IAJIT
2010
13 years 3 months ago
2010
: In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable a...
CORR
2010
Springer
13 years 6 days ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
CORR
2010
Springer
13 years 2 months ago
2010
Springer
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
VLSID
2006
IEEE
13 years 11 months ago
2006
IEEE
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...