174 search results - page 1 / 35 » Reclocking for high-level synthesis |
ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
ASYNC
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...