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» Reconfigurable Instruction Set Processors: A Survey
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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
13 years 10 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ERSA
2004
106views Hardware» more  ERSA 2004»
13 years 7 months ago
QOS Aware HW/SW Partitioning on Run-time Reconfigurable Multimedia Platforms
Advanced multimedia applications (e.g. based on MPEG-4) will consist of multiple scalable multimedia objects. This scalability enables the application to adapt to different proces...
Nam Pham Ngoc, Gauthier Lafruit, Jean-Yves Mignole...
CODES
2003
IEEE
13 years 11 months ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
13 years 11 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
ISCA
2000
IEEE
93views Hardware» more  ISCA 2000»
13 years 9 months ago
Reconfigurable caches and their application to media processing
High performance general-purpose processors are increasingly being used for a variety of application domains scienti c, engineering, databases, and more recently, media processing...
Parthasarathy Ranganathan, Sarita V. Adve, Norman ...