48 search results - page 2 / 10 » Reconfigurable Universal Adder |
TVLSI
2008
13 years 5 months ago
2008
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
SBCCI
2006
ACM
13 years 11 months ago
2006
ACM
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
CODES
1996
IEEE
13 years 9 months ago
1996
IEEE
The partitioning of image processing algorithms with a novel hardware/software co-designframework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Ma...
CORR
2010
Springer
13 years 9 days ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...